1. Field of the Invention
The invention relates in general to a manufacturing method for a semiconductor package, and more particularly to a manufacturing method for a semiconductor package with enhanced routing design flexibility.
2. Description of the Related Art
Referring to FIG. 1, a conventional Quad-Flat Pack (QFN) semiconductor package is shown. The semiconductor package 10 includes a chip 12, a lead frame 14, a plurality of wires 16, a chip base 18, a chip supporting studs 20 and an adhesive 24. The lead frame 14 located on the peripheral of the semiconductor package 10 is exposed from the bottom surface of the semiconductor package 10 to be used as an I/O contact of the semiconductor package 10. The chip 12 is disposed on the chip base 18. The chip base supporting stud 20 supports the chip base 18 to enhance the structural strength of the semiconductor package 10.
However, the wires 16, extended around the semiconductor package 10, are too long and exposed to the risk of short-circuiting. Besides, the lead frame 14, being used as an I/O contact, can only be disposed on the peripheral of the semiconductor package 10, hence limiting the number of the I/O contacts of the semiconductor package 10. Consequently, increasing the number of I/O contacts substantially increases the size of the semiconductor package. Moreover, the lead frame 14 being used as an I/O contact is exposed in the air, and is susceptible to the erosion by the environment.